Hi folks,
I have an issue tuning the IPS / T0SZ / T1SZ settings in TCR_EL1 on rpi4.
For some time I've had MMU enabled in EL1, with page tables working for both TTBR0_EL1 and TTBR1_EL1. Previously I was not interfacing with the VL805 xHCI controller, so was just mapping the 4GB of physical RAM (1:1). I also wanted to add 1:1 virtual-physical mappings for xHCI controller from 0x6 0000 0000 to 0x6 0400 0000. However, in order to do this, I wanted to set IPS bits of TCR_EL1 to 0b100 (address size 36 bits, i.e. 64GB) and T0SZ and T1SZ both to 0b011100. However, this freezes my kernel, and at this point I don't have exception handlers running to see what is up. I could probably delay enabling the MMU until after exception handlers are configured, but I first wanted to check if I am doing something fundamentally wrong, or if there are any other settings that need to be made at the same time.
I have no caching enabled, the previous value of TCR_EL1 (which was successfully working when I only needed to map the 4GB of RAM) was 0x0000000080100010.
The value I wanted to change it to was 0x00000001801c001c (i.e. the changes mentioned above).
I've compared against circle, which I have to say is the most incredible open source project I've ever encountered, a huge shout out to Rene for his incredible work here. Circle uses a different granule size, and doesn't set TTBR1_EL1, so has slightly different values.
Since the issue occurs very early on during startup, it is quite tricky to debug, but on the flip side, it means there isn't too much code to troubleshoot that happens beforehand. From startup until the point of failure is https://github.com/spectrum4/spectrum4/ ... s#L30-L204 (to give an overview of the other system setup).
I guess I initially want to check if there is anything obvious I'm missing, or some fundamental misunderstanding I have. Happy to provide more context if it is useful. Like I say, with just mapping 4GB of physical RAM, everything was working, so the only change desired is to be able a larger address range in order to have access to the VL805 xHCI controller address range too.
Thanks for any tips!
Pete
I have an issue tuning the IPS / T0SZ / T1SZ settings in TCR_EL1 on rpi4.
For some time I've had MMU enabled in EL1, with page tables working for both TTBR0_EL1 and TTBR1_EL1. Previously I was not interfacing with the VL805 xHCI controller, so was just mapping the 4GB of physical RAM (1:1). I also wanted to add 1:1 virtual-physical mappings for xHCI controller from 0x6 0000 0000 to 0x6 0400 0000. However, in order to do this, I wanted to set IPS bits of TCR_EL1 to 0b100 (address size 36 bits, i.e. 64GB) and T0SZ and T1SZ both to 0b011100. However, this freezes my kernel, and at this point I don't have exception handlers running to see what is up. I could probably delay enabling the MMU until after exception handlers are configured, but I first wanted to check if I am doing something fundamentally wrong, or if there are any other settings that need to be made at the same time.
I have no caching enabled, the previous value of TCR_EL1 (which was successfully working when I only needed to map the 4GB of RAM) was 0x0000000080100010.
The value I wanted to change it to was 0x00000001801c001c (i.e. the changes mentioned above).
I've compared against circle, which I have to say is the most incredible open source project I've ever encountered, a huge shout out to Rene for his incredible work here. Circle uses a different granule size, and doesn't set TTBR1_EL1, so has slightly different values.
Since the issue occurs very early on during startup, it is quite tricky to debug, but on the flip side, it means there isn't too much code to troubleshoot that happens beforehand. From startup until the point of failure is https://github.com/spectrum4/spectrum4/ ... s#L30-L204 (to give an overview of the other system setup).
I guess I initially want to check if there is anything obvious I'm missing, or some fundamental misunderstanding I have. Happy to provide more context if it is useful. Like I say, with just mapping 4GB of physical RAM, everything was working, so the only change desired is to be able a larger address range in order to have access to the VL805 xHCI controller address range too.
Thanks for any tips!
Pete
Statistics: Posted by pmoore — Tue Dec 03, 2024 4:36 pm