Well, I'm afraid there's nothing else for it. You'll have to get back to basics and do it the boring way.
Get an A4 sheet of paper and mentally fit the PCB outline within it, viewed from the keys side, looking down. Draw JP1 in its appropriate place, remembering the pin order is mirror imaged because the socket is mounted on the underside of the board. Draw boxes to represent the ICs U1 to U10 in the same relative locations on the paper. Don't worry about the resistor packs, capacitors, or switches.
Now, starting with JP1 pin 1, follow the PCB traces around the board (perhaps through the board) and note them on your diagram. When you have drawn everything that connects to pin 1 do the same for pin 2. If a trace goes under an IC then take your best guess, or just end the line on your drawing.
Next, look at the 16 pins of each IC U1 to U9. Ignore the 8 data pins. Ignore the power and ground pins (although you could confirm that they go to the same place). ~PL should connect to ~PL on all the other chips, and back to JP1. The clock pin should connect to all the other clock pins and back to JP1. Q7 on each chip should connect to DS on the next chip in line, except for the last one, which will connect to JP1.
Probably.
Sketch it out and see how it looks. If there is something quite obviously different to my schematic (which I made up entirely) then that's probably the problem. With a better drawing we have some hope of getting it to work. This is your crash course in reverse engineering. You're doing great.
Get an A4 sheet of paper and mentally fit the PCB outline within it, viewed from the keys side, looking down. Draw JP1 in its appropriate place, remembering the pin order is mirror imaged because the socket is mounted on the underside of the board. Draw boxes to represent the ICs U1 to U10 in the same relative locations on the paper. Don't worry about the resistor packs, capacitors, or switches.
Now, starting with JP1 pin 1, follow the PCB traces around the board (perhaps through the board) and note them on your diagram. When you have drawn everything that connects to pin 1 do the same for pin 2. If a trace goes under an IC then take your best guess, or just end the line on your drawing.
Next, look at the 16 pins of each IC U1 to U9. Ignore the 8 data pins. Ignore the power and ground pins (although you could confirm that they go to the same place). ~PL should connect to ~PL on all the other chips, and back to JP1. The clock pin should connect to all the other clock pins and back to JP1. Q7 on each chip should connect to DS on the next chip in line, except for the last one, which will connect to JP1.
Probably.
Sketch it out and see how it looks. If there is something quite obviously different to my schematic (which I made up entirely) then that's probably the problem. With a better drawing we have some hope of getting it to work. This is your crash course in reverse engineering. You're doing great.
Statistics: Posted by ame — Sat Jun 01, 2024 11:58 pm